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Silicon Labs /BGM220SC12WGA /GPIO_S /PRS0_ASYNCH4ROUTE

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Interpret as PRS0_ASYNCH4ROUTE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PORT 0PIN

Description

ASYNCH4 port/pin select

Fields

PORT

ASYNCH4 port select register
PIN

ASYNCH4 pin select register

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data